Are gate-all-around 2D CFETs the optimal architecture for the A2 node and beyond?

Technical Summary: Are Gate-All-Around 2D CFETs the Optimal Architecture for the A2 Node and Beyond?

Problem Statement
As logic scaling enters the "angstrom era" (A2 node and beyond), classical silicon scaling faces diminishing returns due to severe quantum tunneling, mobility degradation in sub-3 nm channels, and layout-induced constraints on effective channel width ($W_{ch}$). While two-dimensional (2D) semiconductors (e.g., monolayer MoS$_2$, WSe$_2$) offer atomically thin channels with superior electrostatic control, their integration into Complementary Field-Effect Transistors (CFETs) remains unproven at the circuit level. A critical question persists: Does integrating 2D channels into a standard Gate-All-Around (GAA) CFET architecture—optimized for silicon—deliver the necessary performance, power, and area (PPA) gains to meet the A2 node targets, or do integration non-idealities negate the material benefits?

Methodology
The authors employ a multi-scale Design-Technology Co-Optimization (DTCO) framework to evaluate 2D GAA CFETs against the A2 node targets (Contacted Poly Pitch [CPP] = 36 nm, Cell Height [CH] = 42 nm).

1. Integration Flow Definition: A sequential 2D-CFET integration scheme is proposed to overcome bottlenecks in monolithic CFETs, specifically the difficulty of depositing high-$\kappa$/metal gates in narrow vertical gaps. This flow utilizes a wafer flip to process top (NMOS) and bottom (PMOS) devices independently, avoiding high-temperature anneals incompatible with 2D materials and enabling gate-to-gate vias (VGG).
2. Device Modeling:
   • Ab Initio Simulations: Density Functional Theory (DFT) and Non-Equilibrium Green's Function (NEGF) simulations (using ATOMOS) model intrinsic transport in monolayer MoS$_2$ (nFET) and WSe$_2$ (pFET).
   • Compact Modeling: Intrinsic I-V and C-V characteristics are fitted into a BSIM-CMG compact model.
   • Parasitic Extraction: Detailed standard-cell layouts (INVD1) are created for four Design of Experiments (DoE) variants. Parasitic resistance and capacitance are extracted using Synopsys Raphael FX, explicitly incorporating contact resistance ($R_c$) as a series element.
3. Circuit Benchmarking: The models are simulated in a 15-stage fan-out-of-3 (FO3) ring oscillator at $V_{DD}$ = 0.7 V to determine effective switching current ($I_{eff}$) and capacitance ($C_{eff}$). Performance is benchmarked against an A2 iso-frequency target relative to the N2 node.

Key Contributions

• Process Flow Proposal: The paper outlines a feasible sequential integration flow for 2D GAA CFETs, addressing specific challenges such as sacrificial layer removal, channel release without collapse, and conformal metal deposition for source/drain (S/D) contacts.
• Scaling Limit Analysis: The authors demonstrate that despite the atomically thin nature of 2D channels, the minimum CPP for 2D GAA CFETs is constrained to ~36 nm, identical to Si GAA CFETs. This limit is dictated by contact formation constraints (minimum trench width and required sheet protrusion) rather than gate length scaling potential.
• PPA Evaluation Framework: A comprehensive evaluation reveals that while 2D materials offer superior intrinsic electrostatics, the circuit-level performance is dominated by extrinsic factors: high contact resistance and layout-induced parasitic capacitances.

Key Results

• Contact Resistance Bottleneck: The study highlights that achieving low contact resistance ($R_c$) in 2D devices is a primary hurdle. At a state-of-the-art $R_c$ of 42 $\Omega\cdot\mu$m, even the most optimized 2D GAA CFET designs fail to meet the A2 frequency target.
• Parasitic Dominance: As channel width increases to boost drive current, parasitic capacitances (gate, via, and metal wiring) do not scale down proportionally. In baseline designs, parasitic capacitance is roughly six times the intrinsic channel capacitance. While architectural optimizations (e.g., Forksheet structures, separate gate cuts) improve the $I_{eff}/C_{eff}$ ratio, the absolute capacitance overhead remains significant.
• Design Variants (DoE):
  • DoE1 (Baseline): Fails significantly (>50% frequency shortfall) due to narrow channel width and high parasitics.
  • DoE2 & DoE3: Architectural changes (separate gate cuts, Forksheet) improve width and reduce parasitic fractions, bringing performance closer to the target but still falling short at realistic $R_c$.
  • DoE4 (Idealized): Only meets the A2 frequency target under an optimistic assumption of $R_c \le 10 \Omega\cdot\mu$m. At realistic $R_c$ (42 $\Omega\cdot\mu$m), it achieves only ~90% of the target speed.
• Material vs. Architecture: The analysis shows that 2D channels themselves are not the limiting factor; rather, the mismatch between the silicon-optimized GAA CFET architecture and the unique properties of 2D materials (lack of doping, mechanical fragility, contact challenges) prevents the realization of theoretical benefits.

Significance and Claims
The paper concludes that simply inserting 2D channels into a conventional GAA CFET architecture is insufficient to extend Moore's Law to the A2 node and beyond. The expected benefits of 2D materials are "strongly constrained by non-idealities," specifically high contact resistance and dominant parasitic capacitances.

The authors argue that meaningful progress requires a paradigm shift:

1. Co-optimization: Simultaneous optimization of contacts, transport, and parasitics is essential.
2. Architecture Redesign: Future 2D CFETs must move away from strict silicon-optimized templates. The paper suggests exploring "2D-specific CFET architectures" (e.g., hybrid planar-vertical schemes, shared-gate configurations) that decouple electrostatic control from contact formation and reduce architectural overhead.

Ultimately, the paper posits that 2D CFETs remain a credible option for the post-A2 era only if the industry pivots toward architectures specifically designed for the unique constraints of atomically thin materials, rather than forcing them into existing silicon scaling roadmaps.