⚛️ quantum physics

Experimental validation of a compact fault-tolerant architecture for trapped ions

Using a 98-qubit trapped-ion processor, researchers experimentally validated the $[[20,2,6]]$ $C_4$ -Helix architecture by demonstrating repeated quantum error correction, high-fidelity logical Clifford operations, and a fault-tolerant interface to a surface code, all of which outperformed unencoded physical baselines without postselection.

Original authors: Noah Berthusen, Ali Lavasani, Asmae Benhemou, M. S. Allman, Joan Dreiling, Brian Estey, Cameron Foltz, Trent Jacobs, Michael Mills, Annie Jihyun Park, Adam P. Reed, David Hayes, Tzvetan S. Metodi, And

Published 2026-09-04

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Original authors: Noah Berthusen, Ali Lavasani, Asmae Benhemou, M. S. Allman, Joan Dreiling, Brian Estey, Cameron Foltz, Trent Jacobs, Michael Mills, Annie Jihyun Park, Adam P. Reed, David Hayes, Tzvetan S. Metodi, Andrew C. Potter

Original paper licensed under CC BY 4.0 (http://creativecommons.org/licenses/by/4.0/). ✨ This is an AI-generated explanation of the paper below. It is not written or endorsed by the authors. For technical accuracy, refer to the original paper. Read full disclaimer

Technical Summary: Experimental Validation of a Compact Fault-Tolerant Architecture for Trapped Ions

Problem Statement

Quantum error correction (QEC) has recently begun to demonstrate logical operations that outperform unencoded physical counterparts. However, achieving useful fault-tolerant (FT) computation requires more than just low-error memory; it demands an architecture capable of orchestrating efficient logical encoding, low-overhead logical operations, and access to non-Clifford resources for universality. Current high-rate codes often rely on generalized lattice surgery, which introduces significant spatial and temporal overheads. Furthermore, early fault-tolerant regimes require logical error rates (LERs) in the range of $10^{-6}$ to $10^{-8}$ per logical gate, a target that necessitates architectures optimized for both memory protection and computational efficiency on near-term hardware.

Methodology

The authors introduce and experimentally validate a fault-tolerant architecture based on the [[20, 2, 6]] C4-Helix code. This code is a concatenated symplectic double (CSD) code formed by concatenating a [[10, 2, 3]] twisted Toric code with a [[4, 2, 2]] C4 code. The architecture is designed to leverage the arbitrary connectivity of trapped-ion systems to reduce overheads compared to planar topological codes.

The experimental validation was performed on Quantinuum Helios, a 98-qubit trapped-ion quantum processor. The study focused on three principal components of the proposed architecture:

Memory Benchmarking: The authors benchmarked repeated QEC cycles to demonstrate logical error suppression. They prepared logical states, performed 20 rounds of syndrome extraction (mitigating leakage via hardware repumping and circuit-level leakage reduction units), and decoded the data using the Frontier decoder. They compared the performance of the base [[10, 2, 3]] code against the concatenated [[20, 2, 6]] C4-Helix code.
Logical Clifford Benchmarking: To test computational capabilities, the team performed two-qubit randomized benchmarking (TQRB) on the complete logical Clifford group encoded within a single C4-Helix codeblock. This involved interleaving active adaptive syndrome extraction (ASE) with random sequences of logical Clifford gates. The logical gates were compiled using a lookup-table approach that maximizes the use of "free" automorphism gates (implemented via ion transport and qubit relabeling) and minimizes the use of non-automorphism gates (specifically a depth-4 fold-transversal $S_0S_1$ gate).
Heterogeneous Code Interface: To address the need for non-Clifford resources, the authors demonstrated a fault-tolerant interface between the C4-Helix code and a distance-5 rotated surface code. They utilized a chain-map CNOT to prepare a three-logical-qubit GHZ state spanning both code families, effectively testing the "state injection" interface required for universal computation without performing the full magic-state distillation within the C4-Helix code itself.

Key Contributions and Results

1. Logical Error Suppression

The experiment demonstrated that concatenating the [[10, 2, 3]] code with the C4 code successfully suppresses logical errors.

Result: The logical error rate per logical qubit per QEC cycle was reduced from $2.1^{+1.0}_{-0.7} \times 10^{-4}$ for the [[10, 2, 3]] code to $4.6^{+6.2}_{-2.6} \times 10^{-5}$ for the [[20, 2, 6]] C4-Helix code.
Post-selection: By applying forced-gap post-selection (discarding only 0.4% of shots), the error rate was further reduced to $9.3^{+43}_{-7.6} \times 10^{-6}$ .

2. Efficient Logical Clifford Computation

The architecture achieved high-fidelity logical operations without relying on post-selection.

Result: The error per two-qubit logical Clifford gate was measured at $2.8^{+1.0}_{-1.6} \times 10^{-4}$ .
Comparison: This represents a $4.3^{+5.9}_{-1.1} \times$ improvement over the physical unencoded TQRB error rate of $\approx 1.2 \times 10^{-3}$ .
Mechanism: The performance gain was partially attributed to Adaptive Syndrome Extraction (ASE), which reduced the physical two-qubit gate count by 33% and wall-clock time by 23% per shot.

3. Heterogeneous Interface and GHZ Fidelity

The study validated the ability to entangle logical qubits across different code families.

Result: A three-logical-qubit GHZ state was prepared spanning the surface code and C4-Helix code. The logical GHZ fidelity lower bound was $99.925^{+0.068}_{-0.245}\%$ .
Comparison: This exceeds the physical (unencoded) baseline fidelity of $99.54 \pm 0.04\%$ by approximately 0.39%, corresponding to a $6.7\sigma$ separation. This result validates the chain-map CNOT interface as a viable primitive for magic-state injection.

4. Simulation and Scalability

Circuit-level simulations indicate that moderate improvements in physical gate fidelity (already achieved in trapped-ion testbeds) would drive the same [[20, 2, 6]] architecture into the $10^{-6}$ to $10^{-8}$ logical error regime targeted for early fault-tolerant computation.

Significance and Claims

The paper claims to establish the C4-Helix code as a hardware-validated fault-tolerant architecture, rather than merely a quantum memory. The significance lies in the following points:

Compactness and Efficiency: The architecture offers a $\sim 3.5\times$ reduction in spatial overhead compared to conventional rotated surface codes of comparable distance.
Low-Overhead Control: It achieves complete Clifford control with minimal overhead by utilizing transversal gates and automorphisms (qubit relabeling), avoiding the heavy ancilla resources and serialization required by generalized lattice surgery.
Modular Universality: The architecture provides a validated interface for supplying non-Clifford resources from external codes (like surface codes) via chain maps, rather than requiring complex magic-state distillation within the computational code itself.
Hardware Validation: The results demonstrate that a compact, $k > 1$ quantum code can be designed around computational requirements from the outset, successfully outperforming physical baselines in memory, computation, and inter-code entanglement without post-selection.

The authors conclude that while the current experiment does not implement a full universal Clifford+T computation, it successfully establishes the necessary Clifford substrate and heterogeneous interface required to construct one, paving the way for early fault-tolerant quantum computing.