QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation

Digital hardware design is the invisible architecture behind every modern device, from smartphones to satellites. At its core lies a process called Register-Transfer Level design, where engineers translate complex natural language specifications into thousands of lines of precise code that tell a computer chip how to behave. This translation is notoriously difficult and prone to human error, requiring a deep understanding of both logic and language. In recent years, artificial intelligence has shown promise in automating this translation, with large language models capable of writing code based on text descriptions. However, a significant gap has emerged: while these models can handle small, simple tasks, they struggle when faced with the massive, intricate documents that define real-world industrial chips. The sheer volume of information often overwhelms the models, causing them to miss critical details or produce code that fails to function.

A team of researchers has addressed this bottleneck with a new framework called ChipV-RTL, which fundamentally changes how artificial intelligence approaches the generation of hardware code. Instead of asking a single model to read a massive, hundred-page specification and write an entire chip design in one go, the researchers discovered that hardware designs possess a natural quality called "information locality." This means that to write the code for a specific part of a chip, such as a memory controller or a data processor, an engineer only needs to look at the specific section of the document describing that part. They do not need to constantly refer back to the entire document. The researchers realized that by breaking the massive task into smaller, manageable pieces and feeding the model only the relevant text for each piece, they could bypass the confusion that usually plagues these systems.

To test this idea, the team built a multi-agent system that mimics a team of human engineers working together. The process begins by taking a long, detailed design document and splitting it into smaller, organized fragments. A planning agent then breaks the final goal into a series of sub-tasks, assigning each one a specific chunk of the document that contains the necessary instructions. Specialized coding agents then generate the code for each sub-task, working with a focused context that prevents them from getting lost in irrelevant details. Once all the pieces are generated, a merging agent stitches them together into a complete design. Crucially, the system includes a sophisticated debugging loop. If the initial design fails a simulation test, the system uses a structural analysis tool to trace the error back to the exact line of code and the specific sentence in the original document that caused it. It then retrieves only that relevant information to guide the correction, repeating this cycle until the design works perfectly.

The results of this approach were striking when tested against a benchmark of real-world industrial chip designs. In these challenging tests, which involved generating code for complex components like CPU cores and memory controllers, the new framework achieved a success rate of 45 percent. This was more than double the performance of the previous best methods, which managed only about 21.6 percent. The researchers found that the system not only produced code that was more likely to work correctly but also did so with significantly fewer computational resources. By focusing on local information rather than the entire global context, the system avoided the common pitfalls of generating "phantom" signals or mismatched connections that often occur when models try to process too much data at once.

This work suggests that the key to automating complex engineering tasks may not be simply making models larger or smarter, but rather structuring the workflow to align with how the information is naturally organized. The researchers demonstrated that by respecting the modular nature of hardware design, they could turn a problem that was previously too difficult for artificial intelligence into one that it could solve reliably. The framework successfully navigated the intricate debugging cycles required for functional verification, proving that a targeted, locality-aware approach can bridge the gap between theoretical capability and practical application in the high-stakes world of chip design.