A Fully Streaming Low-Latency FPGA Architecture for Range-Doppler SAR Processing Using Radix-2 SDF FFT

Imagine a camera that can see through clouds, rain, and the dead of night, capturing detailed images of the Earth's surface from a moving aircraft or satellite. This is the power of synthetic aperture radar, a technology that has become essential for mapping our planet, monitoring disasters, and guiding autonomous systems. To turn the raw radio signals bouncing off the ground into a clear picture, the data must undergo a complex mathematical transformation known as the Range-Doppler algorithm. This process involves two main steps: first, sharpening the image along the direction the radar beam points, and second, sharpening it along the direction the aircraft is flying. For decades, the standard way to build the computer chips that perform this task has been to wait until the entire image is fully formed in the first step before starting the second. This approach, while simple to manage, creates a significant bottleneck: the machine sits idle, waiting for a massive block of data to be stored and organized before it can begin the next phase of work.

A researcher named Abbas Fadavi has proposed a different way to organize this work, one that eliminates the waiting period entirely. In a study published in August 2026, Fadavi describes a new design for the field-programmable gate array, or FPGA, a type of reconfigurable computer chip often used in high-speed signal processing. Instead of storing the entire intermediate image in a large, centralized memory buffer, the new architecture spreads the necessary storage out across the processing pipeline itself. By carefully arranging the timing of the data flow and using specific types of digital filters, the system allows the second sharpening step to begin the moment the first few pieces of data are ready. This means the two stages of image formation can happen at the same time, rather than one after the other. The result is a processor that delivers the first clear image point much faster and processes the entire image in roughly half the time, without needing more powerful hardware or changing the underlying math.

The core of the problem in traditional radar processing is how data moves through the system. When a radar scans an area, it collects a vast grid of numbers representing the strength of the returned signals. To create a focused image, the computer must perform a series of calculations on these numbers, specifically using a method called the Fast Fourier Transform. In conventional FPGA designs, the computer finishes calculating the first set of sharpening for every single line of the image and stores all those results in a large two-dimensional memory block. Only after this entire block is filled does the computer start the second set of calculations. This creates a long delay because the second half of the processor sits empty while the first half works to fill the memory. It is a bit like a factory assembly line where the first station builds a car and parks it in a massive lot, and the second station cannot start painting the car until the entire lot is full of finished vehicles.

Fadavi's solution removes the parking lot entirely. The new design uses a specific type of digital processor known as a radix-2 single-path delay feedback architecture. In this setup, the memory required to hold data is not a separate, large storage unit but is built directly into the steps of the calculation pipeline. As the data flows through the processor, it passes through small, temporary holding areas that are part of the calculation process itself. By arranging the data flow so that the output of the first calculation stage naturally feeds into the input of the second stage without needing to be reordered or stored in a central block, the system can begin the second stage of processing as soon as the first few data points emerge. This allows the range and azimuth processing to overlap, keeping every part of the machine busy from the very beginning.

The researchers tested this idea by building a complete model of the system and running it on a specific mid-range FPGA chip, the Xilinx Kintex UltraScale. They programmed the chip to handle a standard radar scenario involving 512 lines of data, with each line containing 1,024 samples. The results were striking. In the traditional frame-based approach, the system had to wait 525,824 clock cycles before it could produce the very first output pixel. With the new streaming architecture, that wait time dropped to just 2,048 clock cycles. Furthermore, the total time required to process the entire image frame fell from over 1.05 million clock cycles to roughly 526,000. This represents a reduction of nearly half in the total processing time, achieved not by making the individual calculations faster, but by changing the order in which they happen.

Crucially, the study confirms that this speedup does not come at the cost of accuracy or increased complexity. The researchers verified that the images produced by the new streaming chip were mathematically identical to those produced by the traditional method, with only tiny differences caused by the standard rounding of numbers in digital computers. The design also maintained a steady speed, producing one complete data point every single clock cycle once the initial pipeline was filled. While the total amount of memory used on the chip remained similar to the old design, the way that memory was used changed fundamentally. Instead of acting as a passive storage bin between two separate tasks, the memory became an active part of the continuous flow, holding data only long enough to synchronize the two processing stages.

This work demonstrates that significant performance gains in real-time radar imaging can be achieved through architectural scheduling rather than raw computational power. By reorganizing how data moves through the chip, the researchers created a system that is deterministic, meaning its timing is predictable and consistent, and highly efficient. The findings suggest that future radar systems could deliver images with much lower latency, allowing for faster decision-making in applications where every fraction of a second counts. The study concludes that this streaming approach offers a practical path to overcoming the long-standing delays in synthetic aperture radar processing, proving that sometimes the most effective way to speed up a process is not to work harder, but to work in a different order.